Demand for FeFET is increasing because of its larger storage capacity (e.g., wider memory window) and faster access speed. In a FeFET, switching of the polarization in different directions is caused by applying an electrical field via a voltage between a transistor gate and a transistor channel. A known FeFET includes a ferroelectric high-k layer of a gate stack formed by atomic layer deposition (ALD) on a silicon (Si)/oxide interface that is polycrystalline (i.e., a mixture of different phases wherein not all of the phases are ferroelectric). However, this design results in suboptimal switching properties of the FeFET (program/erase performance) and the Si/oxide substrate is not optimal for ferroelectric growth. As a consequence, there is no degree of freedom to modify the transistor channel. In addition, application of high voltage, e.g., 4 V to 5 V, to the known FeFET gate stack (with a ferroelectric layer over the gate oxide) to read information generates a charge trapping in the gate oxide, which causes irreversible damage because the ferroelectric layer is not in a state to enable switching of the polarization.
A need therefore exists for methodology enabling formation of a ferroelectric layer below a transistor channel and over a buffer layer.